1. Field of the Invention
Embodiments of the present invention relate to DC offset reduction techniques and, in particular, to DC offset reduction techniques that provide improved settling time.
2. Description of Related Art
The performance of electronic devices such as cellular telephones, personal digital assistants and other wireless and wired devices is often related directly to the performance of the components making up the devices. For example, the performance of many wireless devices is often related to the device's receiver that receives and processes transmitted signals. A receiver in a wireless device can be critical to the performance of the device. The receiver is often the first component in the device to see a transmitted signal incident on the device's antenna and, thus, is often the first component to influence the signal. Consequently, the quality of the receiver can be critical to the quality of the performance of the device in general.
A direct conversion receiver circuit typically includes a mixer module for down converting a received signal to a baseband signal, a variable gain amplifier for amplifying the baseband signal, and a signal processing module for processing the baseband signal. Many receivers of this type suffer from inherent inefficiencies. For example, many receivers of this type produce a DC offset in the output of the amplifier that degrades the performance of subsequent processing stages and increases power consumption.
FIG. 1 shows the amplifier stage of a receiver circuit disclosed in U.S. Pat. No. 6,290,226. This amplifier stage is designed to compensate for DC offset in the output signal. The amplifier stage is comprised of a variable gain amplifier 10 that receives the input signal of the amplifier stage, an adder 12, a low pass filter 14, and a variable gain amplifier 16 that provides the output signal of the amplifier stage. A feedback path is provided between the output of the fixed gain amplifier 16 and the adder 12. The feedback path is comprised of a first fixed gain feedback amplifier 18, a capacitor 20, and a second fixed gain feedback amplifier 22. The amount of charge stored in the capacitor controls the output of the fixed gain amplifier 22, which supplies a DC signal to the mixer 12 for compensating DC offset in the output signal. The amount of charge stored in the capacitor for compensating a given DC offset is a function of the DC offset and depends on the gains of the various elements in the loop.
While the circuit of FIG. 1 exhibits an improved settling time, the circuit has certain drawbacks. The circuit of FIG. 1 is essentially a high pass filter that passes high frequency components of the input signal and blocks low frequency components of the signal. The rate of DC offset cancellation provided by this circuit depends on the corner frequency of the high pass pole established by the feedback path. The corner frequency depends on the loop gain of the forward amplification elements and the feedback path elements. Because the gain of the feedback path amplifiers 18, 22 is constant while the gain of the variable gain amplifier 16 is not, the corner frequency of the high pass circuit varies with changes in the gain of the variable gain amplifier 16. In particular, the −3 dB high pass corner frequency of the feedback path is lowered when the gain of the variable gain amplifier 16 decreases, making the settling time of the system longer. Thus the settling time varies inversely with the forward gain of the variable gain amplifier 16. This causes undesirable circuit performance.